The present invention relates to a semiconductor memory used in integrated memory circuits and integrated memory circuits for use with logic devices and more specifically to a ferroelectric random access memory and a chain type ferroelectric random access memory having memory cells of conventional architecture operated at low boost voltages, also to DRAM, a ferroelectric random access memory and a chain type ferroelectric random access having memory cells of conventional architecture operated by a negative word line method or a boosted sense ground method at low boost voltages.
The ferroelectric material has a hysteresis character in the relationship between applied electric field and induced polarization, wherein if the voltage applied across the electrodes of a ferroelectric thin film is returned to zero, some magnitude of polarization remains. Namely, the polarization generated when a voltage was applied is maintained even after the applied voltage has been removed. Another characteristic feature of this material is that if a certain magnitude of inverse voltage is applied, the direction of polarization is accordingly inverted in the ferroelectric material.
With focus on the above characteristics of the ferroelectric material, a ferroelectric random access memory has been developed that has an array of memory cells where the polarization in a ferroelectric thin film is stored as logical information.
There are two representative structures for ferroelectric random access memory cells: a structure in which a ferroelectric thin film is used as an insulative thin film inserted between the two electrodes of a capacitor that holds information; and the other structure in which a ferroelectric thin film is used as the gate insulative film in a MOS transistor used for switching operation.
The former structure is obtained by replacing the capacitor in the DRAM cell with a ferroelectric capacitor. Dipole charge of either two directions of polarity is taken out from the ferroelectric capacitor through a MOS transistor that serves as a transfer gate. Since this operation is a destructive readout, the read data is written back after readout.
The following are the basic structure, characteristics and principles in write/read operations of the former type of ferroelectric random access memory cells.
As types of ferroelectric random access memory cells, there are a 1T1C-type cell of which equivalent circuit is shown in FIG. 25A and a 2T2C-type cell comprising two 1T1C-type cells of which equivalent circuit is shown in FIG. 27A.
In the 1T1C-type cell shown in FIG. 25A, a MOS transistor Q as a transfer gate and a ferroelectric capacitor C serving as memory are electrically connected in series. A word line WL is electrically connected to the gate of the MOS transistor Q, a bit line BL to an electrode (drain) of the MOS transistor Q, and a plate line PL to an electrode (plate) of the capacitor C.
FIG. 25B is a hysteresis loop that explains how the 1T1C-type ferroelectric random access memory cell shown in FIG. 25A reads logical data “0” and “1”, indicating the relationship between a voltage (difference between the plate line voltage VPL and the bit line voltage VBL) applied to a ferroelectric thin film inserted between the electrodes of a ferroelectric capacitor and the magnitude of induced polarization P(C/m). The points “a” and “b” represent the magnitude of remnant polarization.
As hysteresis characteristics shown in FIG. 25B indicate, a cell can represent two different logical states by two residual polarization (Pr) points, “a” and “b”, which are the magnitudes of polarization observed when no voltage (V=0) is applied across the electrodes of the ferroelectric thin film in a ferroelectric capacitor.
Next, the principles of read/write operations in a 1T1C-type ferroelectric random access memory cell are explained with reference to the hysteresis loop shown in FIG. 25B.
First, the bit line voltage VBL is equalized to the ground voltage at the precharge cycle, and then the equalization is released. After the transistor Q is turned on and the word line WL is selected, the plate line voltage VPL is elevated from the ground voltage to the supply voltage to extract the charge stored in the capacitor C to the bit line. The resulting change in the bit line voltage is compared with the reference voltage generated from a cell for reference use and amplified by a sense amplifier (not shown).
When data “0” is read, the polarity in the capacitor C is not inverted and the amount of electric charge read out to the bit line is small. As a result of comparative amplification by the sense amplifier, the bit line (on the side of storage node in the capacitor C) voltage becomes equal to the ground voltage. Thus the polarization of the capacitor C moves from point “a” to point “c” on the hysteresis curve.
On the other hand, when data “1” is read, the polarity in the capacitor C is inverted and the amount of charge read out to the bit line when the supply power voltage is applied as the above plate line voltage VPL is larger than that in the operation of reading “0”. As a result of comparative amplification by the sense amplifier, the bit line (on the side of storage node in the capacitor C) voltage becomes equal to the supply power voltage. Thus the polarization in the capacitor C moves from point “b” to point “c” and then point “a” on the hysteresis curve.
Next, the data latched in the sense amplifier is sent to a data line (not shown) and the plate line voltage VPL is reduced to the ground voltage. Then, the polarization state moves back to point “a” when reading data “0” and moves to point “d” when reading data “1”.
Later, when the transistor Q is turned off, the polarization state moves from point “d” to point “b” when reading “1” and then the rewrite operation to the capacitor C is completed.
The above was an explanation of read/rewrite operations. When new data is written, the voltage equal to the supply power voltage should be applied to the bit line if data “1” is written, and the voltage equal to the ground voltage applied to an input/output line (not shown) if data “0” is written, while the supply power voltage is applied to the plate line.
In the 2T2C-type cell shown in FIG. 26A, a first bit line BL is electrically connected to an electrode of the first transistor Q1 in the first cell, and a second bit line /BL, paired with the first bit line BL, is electrically connected to an electrode of the second transistor Q2 in the second cell. The gates of two transistors Q1 and Q2 have a common word line WL, and the plate electrodes of the two capacitors C1 and C2 have a common plate line PL. The above two bit line BL and /BL are electrically connected to a sense amplifier (not shown) for amplifying the bit line sense voltage and an equalizer circuit (not shown), for example.
Next, the principles of read/write operations in the 2T2C-type ferroelectric random access memory cell are explained.
FIGS. 26A to 26D indicate the applied voltage and the state of polarization in the ferroelectric capacitor during write operation. FIGS. 27A to 27C indicate the applied voltage and the state of polarization in the ferroelectric capacitor during read operation.
FIG. 28 shows the voltage applied to the plate line during above data write and read operations. During write and read operations in the ferroelectric memory cell, the direction of polarization is controlled by changing the plate voltage PL in the selected memory cell as 0V−>3V−>0V, for example.
(A) In the case of writing data, the plate line voltage PL is set to 0V at first, and the voltages of the bit line pair BL and /BL are equalized to 0V. Now it is assumed that the two capacitors C1 and C2 have polarization of which directions are opposite to each other as shown in FIG. 26A.
First, the equalization of the bit lines is released. Next, as shown in FIG. 26B, 4.5V, for example, is applied to the word line WL and the two transistors Q1 and Q2 are turned on. Then 3V, for example, is applied to the plate line PL, and the charges in the capacitors C1 and C2 are read out to the bit line pair BL and /BL. At this moment, a voltage is induced across the electrodes of the capacitor C1 and its polarity is inverted but the polarity of the capacitor C2 is not inverted.
Next, as shown in FIG. 26C, 3V, for example, is applied to either one of the bit lines BL or /BL (/BL, for example), and 0V to the other (BL, for example), and then the plate line PL is returned to 0V as shown in FIG. 26D. As a result, a voltage is induced across the electrodes of the second capacitor C2 and its polarity is inverted but the polarity of the first capacitor C1 is not inverted. Thus polarization with polarity opposite to the initial direction has been written. Later, the word line WL is returned to 0V, and the two transistors Q1 and Q2 are returned to an off state.
(B) In the case of reading data, the plate line PL is set to 0V at first, and the bit line pair BL and /BL are equalized to 0V. It is assumed at this moment that two capacitors C1 and C2 have polarization of which directions are opposite to each other as shown in FIG. 27A.
First, the equalization of the bit lines is released. Next, as shown in FIG. 27B, 4.5V, for example, is applied to the word line WL and the two transistors Q1 and Q2 are turned on. Then 3V, for example, is applied to the plate line PL, and the charges in the capacitors C1 and C2 are read out to the bit line pair BL and /BL. At this moment, a voltage is induced across the electrodes of the second capacitor C2 and its polarity is inverted but the polarity of the first capacitor C1 is not inverted. As a result, the bit line voltage V(BL) becomes lower than the bit line voltage /V(BL). The voltages read from the two capacitors C1 and C2 are amplified by the sense amplifier, and the bit line voltage V(BL) and the bit line voltage /V(BL) become 0V and 3V, respectively, as the output of the sense amplifier.
Then the plate line PL is returned to 0V as shown in FIG. 27C. As a result, a voltage is induced across the electrodes of the second capacitor C2 and its polarity is inverted again but the polarity of the first capacitor C1 is not inverted, returning to the initial state. Later, the word line WL is returned to 0V and the two transistors Q1 and Q2 are returned to an off state.
Such ferroelectric random access memory is under an intensive development effort these years because compared with other types of nonvolatile memory such as flash memory it allows a larger number of rewrites, takes shorter time for write operation, and operates at lower voltages with less power.
Such ferroelectric random access memory with those characteristics is expected to replace conventional memory such as DRAM, flash memory and SRAM. Also its integration with logic devices is raising great expectations. Furthermore, since the ferroelectric random access memory operates with no battery backup and at high speed, its use in non-contacting cards (RF-ID: Radio Frequency-Identification) has started.
On the other hand, if the bit line in the ferroelectric random access memory is made in a folded configuration, its line width cannot be made thinner than 8F2 (F is the minimum design line width). There is another problem that the operation speed of the ferroelectric random access memory is lower than that of DRAM because it drives the plate line containing a large capacity.
To solve those problems, the following papers have been presented to propose new architectures for chain FRAM: VLSI Circuit Sympo. 1997 p. 83-84 “High-Density Chain Ferroelectric Random Access Memory (CFRAM)”; and ISSCC Tech. Dig. Papers, pp. 102-103, February 1999 “A Sub-40 ns Random-Access Chain FRAM Architecture with 7 ns Cell-Plate-Line Drive”.
This type of ferroelectric random access memory has an array of memory cell units comprising two or more serially connected ferroelectric memory cells where the electrodes of the ferroelectric capacitor are electrically connected to the source and the drain of the MOS transistor. Any memory cell can be accessed as desired by turning on the transistors of non-selected cells and turning off the transistor of the selected cell.
According to those papers for chain type ferroelectric random access memory, a higher operation speed and a higher device density are provide, because its cell size becomes a half that of the conventional ferroelectric random access memory and its bit line width becomes ¼ that of the conventional ferroelectric random access memory. The following is a brief explanation of the conventional ferroelectric random access memory.
FIG. 29 is a schematic description of part of the conventional chain type ferroelectric random access memory electric circuit and in particular part of the memory cell array and part of the peripheral circuit.
In FIG. 29, memory cell units are arrayed in line in the memory cell area. In this memory cell unit, more than one memory cell is serially connected of which electrodes in the ferroelectric capacitor are electrically connected to the source and the drain of an enhanced-type (E-type) NMOS transistor.
The present example shows a representative memory cell unit comprising 8 serially connected memory cells, M0-M7 and BM0-BM7. The transistors in those cells, M0-M7, are denoted as Tr0-Tr7, the capacitors as C0-C7, and likewise the transistors in the cells BM0-BM7 are denoted as BTr0-BTr7, and the capacitors as BC0-BC7.
The gates of those transistors Tr0-Tr7 and BTr0-BTr7 are electrically connected to corresponding word lines WLr<0>-WLr<7>, and one electrode of the memory cell unit is electrically connected to the plate line PL<0> or PL<1>. The other electrode is electrically connected to the bit line BL or its complementary bit line BBL through a MOS transistor QB0 or QB1 that is used for selecting a block.
An equalizing circuit EQ, flip-flop-type sense amplifier SA and column selection gate CG are electrically connected to the above bit line pair BL and BBL.
The MOS transistors QB0 and QB2 that are used for selecting a block are controlled by the block select signals V(BSr<0>) and V(BSr<1>), the equalization circuit EQ is controlled by the equalization control signal V(BEQL), the sense amplifier SA is controlled by sense amplifier activation control signals V(SEN) and V(BSEP), and the column selection gate CG is controlled by the column select control signal V(CSL).
However, there is a typical problem in such structure shown in FIG. 29 that the stored polarization is reduced and a disturb takes place during conventional read/rewrite/write operations. This problem is discussed in detail as follows.